Title:
MOS電界効果トランジスタ及びその製造方法
Document Type and Number:
Japanese Patent JP4450490
Kind Code:
B2
Abstract:
A MOSFET device includes a gate formed on a multi-surface area of a semiconductor substrate formed of a first surface which is not etched, a second surface etched in parallel with the first surface, and a surface connecting the first and second surfaces. A source/drain region is formed below each of the first and second surfaces laterally adjacent to a gate prevailed on the matter surface. A first contact is formed of a conductive material formed on an upper surface of the source/drain region, and a second contact is formed of a conductive material formed on the gate, so that it is possible to prevent a punch through phenomenon, increase the integrity of the device, and decrease the contact resistance of a contact formed on the gate.
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| JPS59130442 | MANUFACTURE OF SEMICONDUCTOR DEVICE |
Inventors:
Theon-Jo Park
Yang-Sosun
Yang-Sosun
Application Number:
JP2000228184A
Publication Date:
April 14, 2010
Filing Date:
July 28, 2000
Export Citation:
Assignee:
HYNIX SEMICONDUCTOR INC.
International Classes:
H01L29/78; H01L21/768; H01L21/8234; H01L21/8242; H01L27/108; H01L29/41; H01L29/423; H01L29/49
Domestic Patent References:
| JP53113481A | ||||
| JP57201080A | ||||
| JP7058318A | ||||
| JP4080969A | ||||
| JP7045817A | ||||
| JP8255911A | ||||
| JP58207675A | ||||
| JP2148734A |
Attorney, Agent or Firm:
Eiji Saegusa
Kakehi Yuro
Kimio Matsumoto
Kakehi Yuro
Kimio Matsumoto