Title:
半導体記憶装置
Document Type and Number:
Japanese Patent JP4454925
Kind Code:
B2
Abstract:
A semiconductor memory device comprises a memory cell array, a decoder unit selecting a word line of the memory cell array, a first dummy cell array connected to a first dummy bit line and disposed with the memory cell array at a first location away from the decoder unit along the word line, a second dummy cell array connected to second dummy bit lines and disposed with the memory cell array at a second location away from the decoder unit along the word line, the second location being farther from the decoder unit than the first location, and a timing control unit determining timing of activation and deactivation of an internal control signal.
Inventors:
Tetsuo Ashizawa
Wataru Yokozeki
Wataru Yokozeki
Application Number:
JP2002314567A
Publication Date:
April 21, 2010
Filing Date:
October 29, 2002
Export Citation:
Assignee:
Fujitsu Microelectronics Limited
International Classes:
G11C11/417; G11C7/00; G11C7/22; G11C11/22; G11C11/41; G11C11/413; H01L21/8244; H01L27/10; H01L27/11
Domestic Patent References:
| JP2002056682A | ||||
| JP2000339980A | ||||
| JP1223691A | ||||
| JP3232194A | ||||
| JP2004164772A | ||||
| JP2003323792A | ||||
| JP3495324B2 | ||||
| JP2869336B2 | ||||
| JP4152668B2 | ||||
| JP9198868A | ||||
| JP11203872A | ||||
| JP11203873A |
Attorney, Agent or Firm:
Tadahiko Ito