Title:
半導体素子の製造方法
Document Type and Number:
Japanese Patent JP4467229
Kind Code:
B2
Abstract:
A semiconductor device, capable of precluding the deterioration of flatness and electrical properties due to the non-planarized topology and enhancing oxidative endurance and the process margins, which includes a conductive layer, an insulated layer formed on the conductive layer, a glue layer formed on the insulating layer, a connection unit, which is in contact with the conductive layer through the glue layer and the insulating layer and whose surface is planarized with that of the glue layer and a capacitor including a first electrode formed on the connection unit and the glue layer, a dielectric layer formed on the first electrode and a second electrode formed on the dielectric layer.
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Inventors:
Jun Shou
Ren Win Swing
Cui Yin
Melted
Ren Win Swing
Cui Yin
Melted
Application Number:
JP2002265456A
Publication Date:
May 26, 2010
Filing Date:
September 11, 2002
Export Citation:
Assignee:
HYNIX SEMICONDUCTOR INC.
International Classes:
H01L21/768; H01L21/8242; H01L21/02; H01L21/8246; H01L27/105; H01L27/108; H01L27/115; H01L27/11507; H01L31/0328; H01L31/062
Domestic Patent References:
| JP11040768A | ||||
| JP2000196039A | ||||
| JP2000040800A | ||||
| JP2001308288A |
Attorney, Agent or Firm:
Eiji Saegusa
Kakehi Yuro
Takeshi Ohara
Hiroji Nakagawa
Yasumitsu Tate
Kenji Saito
Jun Fujii
Hitoshi Seki
Mutsuko Nakano
Shinichi Mashita
Ryuji Inuchi
Kakehi Yuro
Takeshi Ohara
Hiroji Nakagawa
Yasumitsu Tate
Kenji Saito
Jun Fujii
Hitoshi Seki
Mutsuko Nakano
Shinichi Mashita
Ryuji Inuchi