To improve productivity by preventing occurrence of human errors in the case of verifying a circuit of an LSI or the like with an algorithm packaged therein.

A CPU interface model 5, a data input interface model 3 and a data output interface model 4 are bus function models corresponding to a CPU interface, a data input interface and a data output interface of a circuit 2, respectively. An input data buffer 6 buffers data to be inputted to the circuit 2 by the CPU interface model 5. The data output interface model 4 compares data outputted from the circuit 2 with an expected value of the output data buffered in an expected value data buffer 7.

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