Title:
ディジタルカメラのアナログ信号処理装置
Document Type and Number:
Japanese Patent JP4477720
Kind Code:
B2
Abstract:
An analog signal processing apparatus for a digital camera includes a correlated double sampling (CDS) circuit adjusting a direct current (DC) level signal from a charge coupled device (CCD) by using a black level as a reference and converting the DC level signal into a typical video signal, an automatic gain control (AGC) circuit automatically adjusting the gain of an output signal of the CDS circuit, an analog-to-digital (A/D) converter converting the analog signal from the AGC circuit into a digital image signal, a black level clamp circuit clamping the black level of the digital image signal from the A/D converter for a predetermined time interval and feeding back the clamped black level to the CDS circuit, and a clock generator generating first and second clock signals and a black level clamping signal so as to control the timing of the black level clamp circuit. The apparatus carries out a black level clamping with regard to the digital image signal that has passed through the A/D converter, thereby solving an offset problem which may occur in the conventional black level clamp circuit and A/D converter and accordingly implementing an accurate black level clamping. Further, a simplified digital comparison circuit is employed instead of a complicated analog comparator, thereby decreasing a chip area and power consumption.
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Inventors:
Min-Kyu Kim
Application Number:
JP31363799A
Publication Date:
June 09, 2010
Filing Date:
November 04, 1999
Export Citation:
Assignee:
MAGNACHIP SEMICONDUCTOR LTD
International Classes:
H04N5/18; H04N5/16; H04N5/222; H04N5/335; H04N5/361; H04N5/378
Domestic Patent References:
| JP6292071A | ||||
| JP8223040A | ||||
| JP9326962A |
Attorney, Agent or Firm:
Tomijio Sasashima
Haruyuki Nishiyama
Moriaki Ogawa
Hiroji Nakagawa
Haruyuki Nishiyama
Moriaki Ogawa
Hiroji Nakagawa