通信バスシステム

Title:

通信バスシステム

Document Type and Number:

Japanese Patent JP4477877

Kind Code:

B2

Abstract:

The bus controller of a bus system supports isochronous messages and non-isochronous messages for which the bus system does and does not support a guaranteed transceiving capacity per time-frame respectively. The system has a first and second memory section for exchange of data from the isochronous messages between a processor and the bus controller. The bus controller has access priority over the processor in alternating first and second ones of the time frames. The bus controller transfers data from isochronous messages between the bus medium and the first and second memory section in the first and second ones of the time frames respectively. The processor has access priority to the first and second memory section over the bus controller in the second and first ones of the time frames respectively. The system contains a third memory section for exchange of data from the non-isochronous messages, a relative access priority of the processor and bus-controller to the third memory section being unchanged in all time frames.

Inventors:

U, Zon-el

Application Number:

JP2003550075A

Publication Date:

June 09, 2010

Filing Date:

November 20, 2002

Export Citation:

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