Title:
半導体素子の銅配線形成方法
Document Type and Number:
Japanese Patent JP4482313
Kind Code:
B2
Abstract:
The present invention relates to a method of forming a copper wiring in a semiconductor device. A copper wiring is formed within a damascene pattern. Before a copper anti-diffusion insulating film is formed on the entire structure, a specific metal element is doped into the surface of the copper wiring and the surface of its surrounding insulating film to form a metal element-doping layer. The doped specific metal element reacts with surrounding other elements, due to heat upon depositing the copper anti-diffusion insulating film and a low dielectric constant interlayer insulating film and additional annealing process. For this reason, a copper alloy layer and a metal oxide layer are stacked at the interface of the copper wiring and the copper anti-diffusion insulating film and the metal oxide layer is formed at the interface of the insulating film and the copper anti-diffusion insulating film. The interfacial bondability between the copper anti-diffusion insulating film and each of the copper wiring and the insulating film underlying the insulating film is increased to improve reliability of the wiring.
Inventors:
Park
Application Number:
JP2003389232A
Publication Date:
June 16, 2010
Filing Date:
November 19, 2003
Export Citation:
Assignee:
MAGNACHIP SEMICONDUCTOR LTD
International Classes:
H01L21/28; H01L21/3205; H01L21/3065; H01L21/44; H01L21/768; H01L23/52; H01L23/522
Domestic Patent References:
| JP2000174027A | ||||
| JP9312291A | ||||
| JP2000058544A | ||||
| JP2002530845A |
Attorney, Agent or Firm:
Hiroyuki Nakagawa