Title:
複数デバイス筐体のテスト方法
Document Type and Number:
Japanese Patent JP4497605
Kind Code:
B2
Abstract:
A self-test method and system for facilitating reliable and fault-tolerant operation of a multi-peripheral-device enclosure (1400) for use in high-availability computer systems. The reliable and fault-tolerant multi-peripheral-device enclosure uses a three-tiered port bypass (1422, 1423, 1426, 1428, 1440, 1442) control strategy for diagnosing and isolating malfunctioning peripheral devices (1402-1409) within the multi-peripheral-device enclosure, and uses a similar a three-tiered port bypass control strategy for isolation of the entire multi-peripheral-device enclosure from a communications medium that interconnects the multi-peripheral-device enclosure with one or more host computers. This three-tiered port bypass control strategy is employed by a self-test routine to isolate the multi-peripheral-device enclosure from external processing elements in order to test peripheral devices and other components within the multi-peripheral-device enclosure, and to isolate any detected defective or malfunctioning components.
Inventors:
Timothy M. Anderson
William Gee Hooper Third
James El White
William Gee Hooper Third
James El White
Application Number:
JP32097799A
Publication Date:
July 07, 2010
Filing Date:
November 11, 1999
Export Citation:
Assignee:
HEWLETT-PACKARD COMPANY
International Classes:
G06F11/22; G06F13/14; G01R31/08; G06F3/06; G06F11/267; G06F11/27
Domestic Patent References:
| JP7503820A | ||||
| JP10285198A | ||||
| JP57069349A |
Foreign References:
| US5812754 | ||||
| US6005696 |
Attorney, Agent or Firm:
Next student Okada