Title:
演算処理装置および演算処理方法
Document Type and Number:
Japanese Patent JP4500358
Kind Code:
B2
Abstract:
In an arithmetic processing apparatus, a dividing unit divides a second bit string into a low-order bit part having a bit width equal to a first bit width and a high-order bit part which is higher than the low-order bit part, a first arithmetic unit performs arithmetic operations for a carry to and a borrow from the high-order bit part; and a second arithmetic unit performs addition of absolute values of the low-order bit part and the first bit string. Finally, a selecting unit selects an output of the first arithmetic unit from among an arithmetic operation result with a carry, an arithmetic operation result with a borrow, and the high-order bit part itself, according to information about the high-order bit part, sign information of the first bit string and the second bit string, and an intermediate result of the addition of the absolute values by the second arithmetic unit.
Inventors:
Ryuji Kan
Application Number:
JP2008501539A
Publication Date:
July 14, 2010
Filing Date:
February 24, 2006
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F7/50
Domestic Patent References:
| JPH02310620A | 1990-12-26 | |||
| JPH038018A | 1991-01-16 | |||
| JP2003196079A | 2003-07-11 |
Attorney, Agent or Firm:
Hiroaki Sakai