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Title:
画素回路及び表示装置
Document Type and Number:
Japanese Patent JP4501059
Kind Code:
B2
Abstract:

To provide a pixel circuit capable of correcting the deterioration of the current-voltage characteristics of a load element with lapse of time in terms of circuits.

A switching transistor Tr 3 turns on during sampling and connects the other end of a holding capacitor Cs to a grounding potential Vss together with a source S of a drive transistor Tr 2, turns off during energizing to a load element EL and disconnects the other end of the holding capacitor Cs from the the grounding potential Vss with the source S of the drive transistor Tr 2, thereby feeding the fluctuation in the source potential of the drive transistor Tr 2 rising accompanying the energizing to the load element EL back to the gate G of the drive transistor Tr 2. The holding capacitor Cs consists of a first capacitor element Cs 1 and second capacitor element Cs 2 of a field effect type which are connected in series to each other by an intermediate node (X). The holding capacitor is equipped with a transistor Tr 3 which sets the potential -Vx necessary for maintaining the field effects of the first capacitor element and the second capacitor element at the intermediate node (X).

COPYRIGHT: (C)2005,JPO&NCIPI


Inventors:
Katsuhide Uchino
Junichi Yamashita
Application Number:
JP2003433630A
Publication Date:
July 14, 2010
Filing Date:
December 26, 2003
Export Citation:
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Assignee:
ソニー株式会社
International Classes:
G09G3/30; H01L51/50; G09G3/20; H05B33/14
Domestic Patent References:
JP2006525539A
JP2003288049A
JP2003223138A
JP2006518473A
JP2006516745A
Attorney, Agent or Firm:
Yoshio Inamoto



 
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