Title:
不揮発性メモリー素子の製造方法
Document Type and Number:
Japanese Patent JP4502801
Kind Code:
B2
Abstract:
Nonvolatile memory device is fabricated by sequentially forming a gate oxide layer (511), polysilicon layer (505, 512) for first control gates, buffer oxide layer, and buffer nitride layer on a semiconductor substrate (501). Fabrication of nonvolatile memory device comprises sequentially forming gate oxide layer, polysilicon layer for first control gates, buffer oxide layer, and buffer nitride layer on a semiconductor substrate; patterning first control gates in the direction of a column by removing some portion of the buffer nitride layer, buffer oxide layer, and polysilicon layer for first control gates; depositing a polysilicon layer for sidewall floating gates (509) over the semiconductor substrate including the first control gate; forming sidewall floating gates on the sidewalls of the first control gates by etching the polysilicon layer for sidewall floating gates; forming common source and drain regions (510) in the semiconductor substrate; removing the sidewall floating gates formed between word lines by patterning the semiconductor substrate in the direction of a row; depositing and planarizing an insulating layer over the semiconductor substrate including the first control gates and the sidewall floating gates so as to fill the gap between the first control gates; removing the buffer nitride layer and the buffer oxide layer on the first control gates; depositing a polysilicon layer for second control gates over the semiconductor substrate including the first control gates and the insulating layer; forming stack gates by removing some portion of the first control gates and the polysilicon layer for second control gates in the direction of a word line; and forming sidewall spacers on the sidewalls of the stack gates. The stack gate includes one first control gate and one second control gate.
Inventors:
Jin Hyo Jun
Application Number:
JP2004380316A
Publication Date:
July 14, 2010
Filing Date:
December 28, 2004
Export Citation:
Assignee:
Dom Electronics Cesik Fesa
International Classes:
H01L21/8247; G11C16/02; H01L21/336; H01L27/105; H01L27/115; H01L29/788; H01L29/792
Domestic Patent References:
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| JP2002124584A | ||||
| JP2003282741A | ||||
| JP2002050703A | ||||
| JP2002190536A | ||||
| JP9116119A | ||||
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Attorney, Agent or Firm:
Takehiko Saito
Yasuyuki Hata
Yasuyuki Hata