To provide a semiconductor device including a plurality of nonvolatile memories in which the operating speed can be enhanced while reducing the area of a peripheral circuit.
This semiconductor device includes a plurality of nonvolatile memories 100 arranged in the row direction and the column direction intersecting the row direction. The nonvolatile memory 100 includes a gate insulation layer 22 provided on the channel region of a semiconductor layer 10, a gate conductive layer 14 provided on the gate insulation layer 22, first conductivity type first and second impurity regions 34 and 24, and a bit conductive layer 80. The bit conductive layer 80 connects the second impurity regions 24 of the memory cell 100 arranged in i rows and [j+1] columns electrically with the first impurity regions 34 of the memory cell 100 arranged in [i+1] rows and [j+1] columns. A charge storage region is provided in the vicinity of one end part of the gate conductive layer 14 in a charge capturing layer 22b and not provided in the vicinity of the other end part thereof.
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Mitsue Obuchi
Misa Nagata