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Title:
マルチプロセッサシステム
Document Type and Number:
Japanese Patent JP4507563
Kind Code:
B2
Abstract:
A splittable/connectible bus 140 and a network 1000 for transmitting coherence transactions between CPUs are provided between the CPUs, and a directory 160 and a group setup register 170 for storing bus-splitting information are provided in a directory control circuit 150 that controls cache invalidation. The bus is dynamically set to a split or connected state to fit a particular execution form of a job, and the directory control circuit uses the directory in order to manage all inter-CPU coherence control sequences in response to the above setting, while at the same time, in accordance with information of the group setup register, omitting dynamically bus-connected CPU-to-CPU cache coherence control, and conducting only bus-split CPU-to-CPU cache coherence control through the network. Thus, decreases in performance scalability due to an inter-CPU coherence-processing overhead are relieved in a system having multiple CPUs and guaranteeing inter-CPU cache coherence by use of hardware.

Inventors:
Naobu Sukegawa
Application Number:
JP2003379294A
Publication Date:
July 21, 2010
Filing Date:
November 10, 2003
Export Citation:
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Assignee:
株式会社日立製作所
International Classes:
G06F12/08; G06F15/167; G06F15/177
Domestic Patent References:
JP2002304328A
JP8320827A
JP8016474A
JP9198309A
JP5108578A
JP10240707A
JP2000250882A
JP9204405A
Other References:
寺澤 卓也 Takuya TERASAWA,計算機の記憶システム-IV,情報処理 第34巻 第1号 Journal of Information Processing Society of Japan,日本,社団法人情報処理学会 Information Processing Society of Japan,1993年 1月,第34巻,p.96-105
寺澤 卓也 Takuya TERASAWA,計算機の記憶システム-IV,情報処理 第34巻 第2号 Journal of Information Processing Society of Japan,日本,社団法人情報処理学会 Information Processing Society of Japan,1993年 2月,第34巻,p.233-243
Attorney, Agent or Firm:
Manabu Inoue