Title:
複数種類のウエルを備えた半導体装置の製造方法
Document Type and Number:
Japanese Patent JP4508606
Kind Code:
B2
Abstract:
A semiconductor device has a configuration in which more than three kinds of wells are formed with small level differences. One kind of well from among the more than three kinds of wells has a surface level higher than other kinds of wells from among the more than three kinds of wells. The one kind of well is formed adjacent to and self-aligned to at least one kind of well from among the other kinds of wells. The other kinds of wells are different in one of a conductivity type, an impurity concentration and a junction depth, and include at least two kinds of wells having the same surface level.
Inventors:
Masaaki Yoshida
Naohiro Ueda
Kijima Masato
Naohiro Ueda
Kijima Masato
Application Number:
JP2003379401A
Publication Date:
July 21, 2010
Filing Date:
November 10, 2003
Export Citation:
Assignee:
株式会社リコー
International Classes:
H01L21/761; H01L21/8238; H01L21/265; H01L21/8239; H01L27/01; H01L27/092
Domestic Patent References:
| JP11330268A | ||||
| JP2138756A | ||||
| JP7106429A | ||||
| JP2003068873A | ||||
| JP2002343884A | ||||
| JP5102427A | ||||
| JP11191616A | ||||
| JP2003258120A | ||||
| JP2000509198A |
Attorney, Agent or Firm:
Shigeo Noguchi