Title:
半導体電力デバイスおよび形成方法
Document Type and Number:
Japanese Patent JP4509562
Kind Code:
B2
Abstract:
In accordance with one embodiment, a stress buffer ( 40 ) is formed between a power metal structure ( 90 ) and passivation layer ( 30 ). The stress buffer ( 40 ) reduces the effects of stress imparted upon the passivation layer ( 30 ) by the power metal structure ( 90 ). In accordance with an alternative embodiment, a power metal structure ( 130 A) is partitioned into segments ( 1091 ), whereby electrical continuity is maintained between the segments ( 1090 ) by remaining portions of a seed layer ( 1052 ) and adhesion/barrier layer ( 1050 ). The individual segments ( 1090 ) impart a lower peak stress than a comparably sized continuous power metal structure ( 9 ).
Inventors:
Mercado, Ray Elle.
Sarihan, Vijay
Chun, Yong Sir
One, James Jen-Ho
Pluck, Edward Earl.
Sarihan, Vijay
Chun, Yong Sir
One, James Jen-Ho
Pluck, Edward Earl.
Application Number:
JP2003550276A
Publication Date:
July 21, 2010
Filing Date:
November 13, 2002
Export Citation:
Assignee:
Freescale Semiconductor, Inc.
International Classes:
H01L21/60; H01L21/768; H01L23/31; H01L23/485; H01L23/532
Domestic Patent References:
| JP2000091339A | ||||
| JP2001168126A | ||||
| JP2000243771A | ||||
| JP8213422A | ||||
| JP10233507A |
Foreign References:
| WO2000077843A1 |
Attorney, Agent or Firm:
Mamoru Kuwagaki