To provide a storage device in which problems associated with write disturbance and read disturbance are resolved and reliability is improved.
When data are to be written into a phase change memory, the data are temporarily read in a step S4. Then, it progresses to a step S5 and discrimination is made to determine whether the read data are "1" or "0". When the read data are "0", it progresses to a step S6 and a current is applied to a memory cell to write "1". On the other hand, it is judged that the read data are "1" in the step S5, no writing operation is conducted and it advances to a step S10. Desirably, no data reading is conducted and data "0" are written when the writing data are "0". Since no re-writing of "1" is conducted to a high resistive state (the state in which "1" is held), the resistive ratio of the memory cell is made greater, the reading output signals are made larger and the reading access time is made faster.
COPYRIGHT: (C)2005,JPO&NCIPI
| JP2003502791A |
| WO2003065377A1 |
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Masayuki Sakai
Nobuo Arakawa
Masato Sasaki
Hisato Noda