Title:
ビット線ダミーコアセル
Document Type and Number:
Japanese Patent JP4541391
Kind Code:
B2
Abstract:
A bit line dummy core-cell comprises at least a first inverter and at least a second inverter which are cross coupled to form a bistable flip-flop. The first inverter comprises a first PMOS transistor and a first NMOS transistor connected in series by means of a first internal storage node between a high reference potential and a low reference potential. The second inverter comprises a second PMOS transistor and a second NMOS transistor connected in series by means of a second internal storage node. The source of the second PMOS transistor and the second internal storage node are connected to the low reference potential so that the first internal storage node always stores a logic high level. A first access transistor is coupled between a dummy bit line providing a self-timing signal and the first internal node storing the logical high level.
Inventors:
Christoph Shanuso
Vincent Guang
Alexander Olbrich
Martin Ostermeier
Vincent Guang
Alexander Olbrich
Martin Ostermeier
Application Number:
JP2007273890A
Publication Date:
September 08, 2010
Filing Date:
October 22, 2007
Export Citation:
Assignee:
Infineon Technologies AG
International Classes:
G11C11/41; G11C11/413; G11C11/417; H01L21/8244; H01L27/11
Domestic Patent References:
| JP2003036678A | ||||
| JP2004220721A | ||||
| JP2002367377A |
Attorney, Agent or Firm:
Kenzo Hara International Patent Office