Title:
判定帰還型等化器における帰還ループ遅延に関連する性能損失を軽減する回路及び方法
Document Type and Number:
Japanese Patent JP4542775
Kind Code:
B2
Abstract:
A decision feedback equalizer (DFE) includes a forward equalizer, first and second adders, a decision device, a feedback equalizer, and an N-tap filter. Preferably, the first and second adders, the decision device, and the feedback equalizer constitute a first feedback loop, the second adder, the decision device, and the N-tap filter constitute a second feedback loop. In that case, the second feedback loop is free of an implementation delay associated with the first feedback loop. In the exemplary DFE, N is a positive integer. If desired, the N-tap filter is implemented in fast logic. A method for controlling a decision feedback equalizer based on first and second feedback signals is also described.
Inventors:
BILL DAGNAKEU
Application Number:
JP2003501159A
Publication Date:
September 15, 2010
Filing Date:
May 28, 2002
Export Citation:
Assignee:
NXP B.V.
International Classes:
H04B7/005; H04B3/06; H04L25/03
Domestic Patent References:
| JP5502765A | ||||
| JP2000507067A | ||||
| JP3159424A |
Foreign References:
| US5748674 |
Attorney, Agent or Firm:
Kenji Sugimura
Tatsuya Sawada
Tatsuya Sawada