Title:
半導体デバイスパッケージ及びその半導体デバイスパッケージを有する半導体デバイスアセンブリ
Document Type and Number:
Japanese Patent JP4550173
Kind Code:
B2
Abstract:
A semiconductor device package for one or more semiconductor dice having core circuits and input-output circuits uses a package substrate having one pair of biplanar conductive planes and another pair of biplanar conductive planes. The pairs of planes are positioned in a coplanar relationship between the package substrate top surface and bottom surface. The top surface has lands connected to the conductive planes and to the power bond pads for the core circuits and input-output circuits on the semiconductor die. The top surface has many top traces connected to the signal bond pads on the semiconductor die. The package substrate may have a die paddle connected to one land and/or thermal vias to conduct heat away from the semiconductor die. Power may be supplied to die core circuits through one pair of planes and to die input-output circuits through another pair of planes to decouple the core circuits from the input-output circuits and minimize noise induced false switching in either set of circuits. The core circuits and the input-output circuits may be powered by the same power supply or separate power supplies.
Inventors:
Thai-You Chow
Sanjay Dandia
Sanjay Dandia
Application Number:
JP15803397A
Publication Date:
September 22, 2010
Filing Date:
May 30, 1997
Export Citation:
Assignee:
LSI LOGIC CORPORATION
International Classes:
H01L23/12; H01L23/498
Domestic Patent References:
| JP6338571A | ||||
| JP6140529A |
Attorney, Agent or Firm:
Shoichi Okuyama
Arihara Koichi
Arihara Koichi