Title:
データ受信機および送信機におけるタイミング制御
Document Type and Number:
Japanese Patent JP4554934
Kind Code:
B2
Abstract:
A Gigabit transceiver ( 1 ) has a receiver ( 2 ) and a transmitter ( 3 ). There is an ADC ( 5 ) in the receiver ( 2 ) for each channel (A, B, C, D). The ADCs ( 5 ) oversample at a factor of 2. However the remainder of the digital circuitry and transmitter DACs ( 2 ) operate off half of the oversampling rate. In the receiver ( 2 ) fractionally spaced equalisers (FSES, 6 ) ensure that the optimum sampling phase is selected digitally. The invention avoids the need for a PLL in the receiver for each channel and associated interference and retiming problems.
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Inventors:
Molina, Navarro, Albert
Bates, stephen
Karen, Philip
Murray, Karl, Damien
Bates, stephen
Karen, Philip
Murray, Karl, Damien
Application Number:
JP2003559096A
Publication Date:
September 29, 2010
Filing Date:
December 11, 2002
Export Citation:
Assignee:
Agia Systems (Ireland) Research Limited
International Classes:
H04B3/06; H04L25/02; H04L7/00; H04L7/02; H04L25/03; H04L25/08; H04L25/14; H04L7/033
Domestic Patent References:
| JP2000341123A | ||||
| JP2001156866A |
Foreign References:
| WO1999046867A1 | ||||
| WO2001006774A1 |
Other References:
802.3ab-199,IEEE Standard,米国,IEEE,1999年,pages.15-18
Attorney, Agent or Firm:
Masao Okabe
Nobuaki Kato
Kazuo
Shinichi Usui
Takao Ochi
Teruhisa Motomiya
Asahi Shinmitsu
Katsumi Miyama
Nobuaki Kato
Kazuo
Shinichi Usui
Takao Ochi
Teruhisa Motomiya
Asahi Shinmitsu
Katsumi Miyama