Title:
半導体素子のキャパシタ製造方法
Document Type and Number:
Japanese Patent JP4556293
Kind Code:
B2
Abstract:
The present invention discloses a method for fabricating a capacitor of a semiconductor device. In the conventional art, a bit line may be shifted or bent differently from the definition on a mask due to the stress resulting from a material difference between the bit line and BPSG film. However, in the present invention, the bit line is formed after depositing an oxide material on a contact plug, thereby preventing the shift or bending phenomenon and the short phenomenon between the metal interconnection contact and bit line. As a result, an open area is obtained during the formation step of a storage electrode, the insulating property between the bit line and storage electrode improves during the self aligned contact (SAC) etching step for forming a storage electrode contact hole, and the high speed and high integration of the semiconductor device are achieved by obtaining a sensing margin of the semiconductor device due to the capacitance reduction of the bit line, thereby enhancing a process yield and properties of the semiconductor device.
Inventors:
Lee
Golden bell
Golden bell
Application Number:
JP2000187818A
Publication Date:
October 06, 2010
Filing Date:
June 22, 2000
Export Citation:
Assignee:
HYNIX SEMICONDUCTOR INC.
International Classes:
H01L21/768; H01L21/8242; H01L21/60; H01L27/10; H01L27/108; H01L21/02
Domestic Patent References:
| JP9181270A | ||||
| JP9223777A | ||||
| JP11026718A | ||||
| JP10079491A | ||||
| JP8125141A | ||||
| JP10079480A | ||||
| JP10214948A | ||||
| JP7231045A |
Attorney, Agent or Firm:
Keiichi Yamamoto