Title:
DLL回路
Document Type and Number:
Japanese Patent JP4558347
Kind Code:
B2
Abstract:
A DLL circuit comprises a dummy delay corresponding to an internal clock delay from an external clock, a variable delay addition circuit having a coarse and fine delay circuits adjusting delay amount according to a delay amount adjustment signal, and a phase comparison circuit comparing phases of the internal clock and a delay clock input via the variable delay addition circuit and the dummy delay and outputting the delay amount adjustment signal to the variable delay addition circuit. At the start of burst, a first signal set at a logic "1" during 1 clock cycle of the internal clock is input to the variable delay addition circuit via the dummy delay, and duration time of the logic "1" of the first signal is detected until 1 clock cycle of the internal clock is completed and delay amount of the variable delay addition circuit is initialized by setting one of the coarse delay circuit based on the duration time.
Inventors:
Makoto Hirano
Shinji Matoba
Shoichi Ohori
Nishiyama Masashi
Hiroshi Takashima
Masamichi Asano
Kengo Maeda
Akira Tanikawa
Shinji Matoba
Shoichi Ohori
Nishiyama Masashi
Hiroshi Takashima
Masamichi Asano
Kengo Maeda
Akira Tanikawa
Application Number:
JP2004053774A
Publication Date:
October 06, 2010
Filing Date:
February 27, 2004
Export Citation:
Assignee:
Toppan Printing Co., Ltd.
Sharp Corporation
Sharp Corporation
International Classes:
G11C16/02; G01F1/12; G06F1/10; G11C11/4063; G11C11/4076; G11C16/32; H03H11/26; H03K5/13; H03K5/1534; H03L7/08; H03L7/081
Domestic Patent References:
| JP2000076852A | ||||
| JP11273342A | ||||
| JP4105411A | ||||
| JP2002123873A |
Attorney, Agent or Firm:
Masatake Shiga
Tadashi Takahashi
Takashi Watanabe
Masakazu Aoyama
Suzuki Mitsuyoshi
Kazuya Nishi
Yasuhiko Murayama
Tadashi Takahashi
Takashi Watanabe
Masakazu Aoyama
Suzuki Mitsuyoshi
Kazuya Nishi
Yasuhiko Murayama