Title:
半導体装置の製造方法
Document Type and Number:
Japanese Patent JP4559866
Kind Code:
B2
Abstract:
A semiconductor device of the present invention includes a plurality of lower electrodes covering the entire surfaces of a plurality of trenches formed in a first interlayer insulating film, a capacitive insulating film covering the entire surfaces of the plurality of lower electrodes, and an upper electrode covering the surfaces of the plurality of lower electrodes from above with the capacitive insulating film interposed between the upper electrode and the plurality of lower electrodes. The upper electrode is formed with a stress-relieving part, such as a crack, a notch or a recess.
Inventors:
Yoshiyuki Shibata
Application Number:
JP2005009269A
Publication Date:
October 13, 2010
Filing Date:
January 17, 2005
Export Citation:
Assignee:
Panasonic Corporation
International Classes:
H01L21/8242; H01L27/108
Domestic Patent References:
| JP11026712A | ||||
| JP2002343889A | ||||
| JP2002083880A | ||||
| JP2002252351A | ||||
| JP2000183214A | ||||
| JP2003332468A | ||||
| JP10064852A | ||||
| JP2000373945A |
Attorney, Agent or Firm:
Hiroshi Maeda
Hiroshi Koyama
Hiroshi Takeuchi
Takahisa Shimada
Yuji Takeuchi
Katsumi Imae
Atsushi Fujita
Kazunari Ninomiya
Tomoo Harada
Iseki Katsumori
Hiroshi Koyama
Hiroshi Takeuchi
Takahisa Shimada
Yuji Takeuchi
Katsumi Imae
Atsushi Fujita
Kazunari Ninomiya
Tomoo Harada
Iseki Katsumori