電界型単電子箱多値メモリ回路およびその制御方法 - Nippon Telegraph and Telephone Corporation

Title:

電界型単電子箱多値メモリ回路およびその制御方法

Document Type and Number:

Japanese Patent JP4571396

Kind Code:

B2

Abstract:

To accurately control stored elementary charge one by one, realize multi-level by expressing one information by one elementary charge and reduce the time required for storage and erase.

In a controlling FET connected between a single electronic box 3 and an electrode ER, the charge amount inside the single electronic box 3 is adjusted by moving the charge amount in accordance with a charge adjusting voltage between the electrode ER and the single electronic box 3 by switching a channel, and a detected current in accordance with the charge amount stored in the single electronic box 3 is made to flow to the channel by a detecting FET2 with a channel which is subjected to capacity junction to the single electronic box 3.

Inventors:

Katsuhiko Nishiguchi
Hiroshi Inokawa
Yukinori Ono
Satoshi Fujihara
Yoshio Takahashi

Application Number:

JP2003413666A

Publication Date:

October 27, 2010

Filing Date:

December 11, 2003

Export Citation:

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Assignee:

Nippon Telegraph and Telephone Corporation

International Classes:

H01L27/10; H01L29/06; H01L29/66; H01L29/786

Domestic Patent References:

JP10093109A

Other References:

高橋庸夫 Y Takahashi,単電子トランジスタとMOSFETを組み合わせたSiメモリデバイス,応用物理学関係連合講演会講演予稿集1998春1 Extended Abstracts (The 45th Spring Meeting, 1998);The Japan Society of Applied Physics and Related Societies No.1,日本,(社)応用物理学会,1998年 3月,p.189,30p-YE-4

Attorney, Agent or Firm:

Masaki Yamakawa
Hiroro Kurokawa
Shigeki Yamakawa

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