Title:
電子部品パッケージの製造方法ならびに電子部品パッケージの製造に用いられるウェハおよび基礎構造物
Document Type and Number:
Japanese Patent JP4577788
Kind Code:
B2
Abstract:
A wafer for electronic component packages is used for manufacturing a plurality of electronic component packages, each of the plurality of electronic component packages including: a base incorporating a plurality of external connecting terminals; and at least one electronic component chip bonded to the base and electrically connected to the plurality of external connecting terminals. The wafer has a plurality of sets of external connecting terminals corresponding to the plurality of electronic component packages, a retainer for retaining the plurality of sets of external connecting terminals, and a coupling portion for coupling the plurality of sets of external connecting terminals to one another. The wafer includes a plurality of pre-base portions that will each be subjected to bonding of the at least one electronic component chip thereto and will be subjected to separation from one another later so that each of them will thereby become the base.
Inventors:
Yoshitaka Sasaki
Tatsushi Shimizu
Tatsushi Shimizu
Application Number:
JP2007216732A
Publication Date:
November 10, 2010
Filing Date:
August 23, 2007
Export Citation:
Assignee:
Headway Technologies, Inc.
International Classes:
H01L25/04; H01L23/52; H01L25/18
Domestic Patent References:
| JP2003163324A | ||||
| JP3247384B2 |
Attorney, Agent or Firm:
Katsumi Hoshimiya
Kazuhiro Watanabe
Kazuhiro Watanabe