Title:
試験シミュレータ及び試験シミュレーションプログラム
Document Type and Number:
Japanese Patent JP4580722
Kind Code:
B2
Abstract:
A test simulator for simulating a test of a semiconductor device is disclosed, the test simulator including: a test pattern holding unit for holding an existing test pattern to be supplied to the semiconductor device; a device output holding unit for preliminarily holding an output to be obtained from the semiconductor device when the existing test pattern is supplied; a test pattern generating unit for generating a new test pattern to be supplied to the semiconductor device; a test pattern deciding unit for deciding whether the new test pattern is equal to the existing test pattern; and a simulation skipping unit for skipping at least a part of a simulation test by reading an output from the device output holding unit and using the output as an output for the new test pattern without supplying the new test pattern to the semiconductor device when the test patterns are equal to each other.
Inventors:
Hideki Tada
Hori Mitsuo
Takahiro Kataoka
Hori Mitsuo
Takahiro Kataoka
Application Number:
JP2004278582A
Publication Date:
November 17, 2010
Filing Date:
September 24, 2004
Export Citation:
Assignee:
Advantest Corporation
International Classes:
G01R31/28
Domestic Patent References:
| JP2003315419A | ||||
| JP3061871A |
Attorney, Agent or Firm:
Akihiro Ryuka