Title:
オーバーレイエラーを測定するための半導体デバイス、オーバーレイエラーを測定するための方法、リソグラフィ装置、およびデバイス製造方法
Document Type and Number:
Japanese Patent JP4584967
Kind Code:
B2
Abstract:
A semiconductor device for determining an overlay error on a semiconductor substrate includes a first and a second transistor. Each transistor includes two diffusion regions associated with a gate, the diffusion regions of each transistor being arranged in a first direction. The second transistor is arranged adjacent to the first transistor in a second direction perpendicular to the first direction. The first and second gate each have a non-uniform shape, and the second gate is oriented with respect to an orientation of the first gate in such a way that an effect of an overlay error on a device parameter of the second transistor has an opposite sign in comparison to an effect of the overlay error on the device parameter of the first transistor.
Inventors:
Dusa, Mercy
Knackers, accelerator
Bellhagen, gustav
Knackers, accelerator
Bellhagen, gustav
Application Number:
JP2007228801A
Publication Date:
November 24, 2010
Filing Date:
September 04, 2007
Export Citation:
Assignee:
AS M Netherlands B.V.
International Classes:
H01L21/027; G03F9/00
Domestic Patent References:
| JP9162100A | ||||
| JP10062809A | ||||
| JP9251945A | ||||
| JP2003172601A | ||||
| JP61224429A | ||||
| JP7029952A | ||||
| JP2004214638A |
Attorney, Agent or Firm:
Yoshiyuki Inaba
Shinji Oga
Toshifumi Onuki
Shinji Oga
Toshifumi Onuki