Title:
シリコン-ゲルマニウムゲートを持つトランジスタを得るための方法
Document Type and Number:
Japanese Patent JP4601734
Kind Code:
B2
Abstract:
Production of an IGFET with a Si1-xGex (x = greater than 0 and ≤ 1, preferably 0.5-1) gate involves subjecting a semiconductor substrate (SB), having an active zone (ZA) and an overlying gate oxide layer (1), to (a) treatment in a single wafer reactor for CVD at ≤ 580 degrees C of a ≤ 1 nm thick silicon bond layer (2) on the gate oxide layer and then for CVD at ≤ 550 degrees C of a stack comprising a first continuous Si1-xGex layer (3) and an overlying second silicon layer (4); (b) gate (GR) production by depositing and etching an upper inorganic material layer (5) on the stack to obtain an inorganic mask, etching the stack using the mask to form the gate region (GR) and then depositing an encapsulation layer (7) of material which does not oxidise germanium; and (c) formation, on the encapsulated gate sidewalls, of insulating regions (8) of material which does not oxidise germanium.
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Inventors:
Isabelle sagne
Application Number:
JP17874998A
Publication Date:
December 22, 2010
Filing Date:
June 25, 1998
Export Citation:
Assignee:
FRANCE TELECOM
International Classes:
C23C16/22; H01L29/78; H01L21/28; H01L21/3065; H01L21/3213; H01L29/423; H01L29/49
Domestic Patent References:
| JP7202178A | ||||
| JP8186256A |
Other References:
Neal Kistler et al.,SYMMETRIC CMOS IN FULLY-DEPLETED SILICON-ON-INSULATOR USING P+-POLYCRYSTALLINE Si-Ge GATE ELECTRODES,IEDM'93,1993年,PP.727-730
Attorney, Agent or Firm:
Nozomi Watanabe
Haruko Sanwa
Haruko Sanwa