Title:
エッジ・ダイ上の一様性及び平坦性を改善しウエハのCMPに起因するタングステン・ストリンガを除去する新規な方法
Document Type and Number:
Japanese Patent JP4620189
Kind Code:
B2
Abstract:
A process of making an IC wafer including a surface with improved uniformity, planarity and a reduced likelihood of creating stringers is disclosed. The process includes: depositing a layer of polysilicon or metallization on the surface having a die region including a plurality of die that are disposed interior to a perimeter of the surface and a peripheral region disposed outside the die region and abutting the die region of the surface; depositing a layer of photoresist on the layer of metallization; exposing the layer of photoresist to radiation to define a mask on an area in the die region and designated to form the plurality of die; exposing at least a portion of the layer of photoresist to radiation to define the mask in the peripheral region of the wafer surface; and etching the layer of metallization underlying unmasked portions of the photoresist in the peripheral region along with the die region of the surface to limit material build-up on the peripheral region and form metal contact regions underlying the masked portions.
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Inventors:
Kuppam E. Kumar
Application Number:
JP35561697A
Publication Date:
January 26, 2011
Filing Date:
December 24, 1997
Export Citation:
Assignee:
LSI LOGIC CORPORATION
International Classes:
H01L21/302; H01L21/02; H01L21/304; H01L21/027; H01L21/3065; H01L21/3205; H01L21/321; H01L21/3213
Domestic Patent References:
| JP62195119A | ||||
| JP3070119A | ||||
| JP4101146A | ||||
| JP4291914A | ||||
| JP5114537A | ||||
| JP5217834A | ||||
| JP6005508A | ||||
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| JP9232259A | ||||
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| JP6045287A | ||||
| JP3084921A | ||||
| JP6020903A |
Attorney, Agent or Firm:
Kazuo Shamoto
Tadashi Masui
Yasushi Kobayashi
Akio Chiba
Hiroyuki Tomita
Otsuka Sumie
Tadashi Masui
Yasushi Kobayashi
Akio Chiba
Hiroyuki Tomita
Otsuka Sumie