To obtain a defect analysis method capable of improving measurement throughput and acquiring correct analysis results.

In a step S1, defect detection processing is performed for extracting a novel defect coordinate and a detection size by a predetermined process after the predetermined process through the use of an area reducing function of a tester. In a step S3, whether the novel defect exists or not is determined for each chip under identification conditions that all of the detected novel defects are effective. Thereafter, in a step S5, the area ratio of a region to be checked for a fault by the area reducing function to all regions where the fault inspection is possible is calculated. In a step S6, the number of chips with estimated faults is estimated and converted on the basis of the area ratio.

COPYRIGHT: (C)2005,JPO&NCIPI