Title:
プログラマブルロジック集積回路デバイスの相互接続ならびに入力/出力リソース
Document Type and Number:
Japanese Patent JP4637790
Kind Code:
B2
Abstract:
A programmable logic integrated circuit device (10) has a plurality of regions (20) of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources (200a, 210a, 230a) may have what may be termed normal signal speed, while a smaller minor portion (200b, 210b, 230b) may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.
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Inventors:
Tony Nguy
Bruce Pederson
Sergey Schuma Rave
James shreker
Way-Jen Hyun
Michael hatton
Victor Maruri
Rakesh patel
Peter Jay Kazarian
Andrew Reaver
David W Mendel
Jim Park
Bruce Pederson
Sergey Schuma Rave
James shreker
Way-Jen Hyun
Michael hatton
Victor Maruri
Rakesh patel
Peter Jay Kazarian
Andrew Reaver
David W Mendel
Jim Park
Application Number:
JP2006146010A
Publication Date:
February 23, 2011
Filing Date:
May 25, 2006
Export Citation:
Assignee:
Altera Corporation
International Classes:
H03K19/177; H03K19/173
Domestic Patent References:
| JP8237109A | ||||
| JP9181598A |
Foreign References:
| WO1998043354A1 |
Attorney, Agent or Firm:
Hidesaku Yamamoto
Takaaki Yasumura
Natsuki Morishita
Takaaki Yasumura
Natsuki Morishita