Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
半導体デバイス内のスクライブストリートシール及び製造方法
Document Type and Number:
Japanese Patent JP4647061
Kind Code:
B2
Abstract:
An integrated circuit wafer, covered by a protective overcoat, comprising an array of integrated circuit chips bordered by seal regions and separated by dicing lines; at least two sets of substantially parallel structures within each of said seal regions, each set extending along the edge of a chip on opposite sides of each said dicing line, respectively; each of said sets comprising at least one continuous barrier wall adjacent each chip, respectively; at least one sacrificial composite structure in combination therewith, between said wall and the center of said dicing line, said composite structure being a discontinuous barrier wall comprising metal rivets interconnecting electrically conductive layers in an alternating manner, whereby said composite structure provides mechanical strength to said sets and simultaneously disperses the energy associated with crack propagation; and at least one slot opened into said protective overcoat, reaching from the surface of said overcoat at least to the surface-nearest electrically conductive layer of said composite structure, whereby cracks propagating in said protective overcoat will be stopped.

Inventors:
Jeffrey A West
Paul M Gillespie
Application Number:
JP2000149751A
Publication Date:
March 09, 2011
Filing Date:
May 22, 2000
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
Texas Instruments Incorporated
International Classes:
H01L21/301; H01L23/00; H01L23/04; H01L23/58
Domestic Patent References:
JP2000232081A
JP10022236A
JP10098014A
JP9266209A
JP6163688A
JP10270388A
JP1309351A
JP8037289A
Foreign References:
US5831330
US20020024115
Attorney, Agent or Firm:
Minoru Nakamura
Fumiaki Otsuka
Sadao Kumakura
Shishido Kaichi
Hideto Takeuchi
Toshio Imajo
Nobuo Ogawa
Village shrine Atsuo
Takaki Nishijima
Atsushi Hakoda