To resolve a problem in a path with no margin in timing when carrying out a delay test wherein the number of flip-flops of a start point is not necessarily one with respect to a flip-flop that is an end point, and depending on a combination circuit precedent to a flip-flop that is another start point, in some cases, transition of a logic value in a scanning flip-flop inverting an output bit that is a start point does not propagate to an observation point, and a delay failure test cannot be carried out.

A retention facilitated type scanning flip-flop retaining an output value is prepared, and a flip-flop not on a target path of all flip-flops relevant to a flip-flop to be an end point of the test target path is replaced by a retention facilitating circuit retaining the output value. By this, other paths are deactivated during delay failure detection (a delay test) of the target path, and change of a signal in an inversion facilitated type scanning flip-flop which is a start point of the target path is positively propagated to a test target circuit.

COPYRIGHT: (C)2006,JPO&NCIPI