Title:
不揮発性半導体記憶装置
Document Type and Number:
Japanese Patent JP4657813
Kind Code:
B2
Abstract:
Disclosed is to enable high speed reading from a storage node when a read is executed. A main cell array is constituted from main cell division units 20a. Each main cell division unit 20a includes select gates SG that extend in a vertical direction, common sources CS that extend in a horizontal direction below the select gates SG outside a cell region, word lines W0 to W15 that extend above the select gates SG in the horizontal direction within the cell region, a plurality of storage nodes disposed in the vicinity of intersecting portions between the word lines W0 to W15 and the select gates SG, respectively, below the word lines W0 to W15, and a bit line MGB for transmitting to a sense amplifier 11 information on one of the storage nodes through a selection switch 21. In the main cell division unit 20a, an inversion layer is formed below each of the select gates SG within the cell region by applying a positive voltage to each of the select gates SG. A reference cell array is constituted from a reference cell division unit 30a having a same configuration as the main cell division unit 20a.
Inventors:
Naoaki Sudo
Application Number:
JP2005160346A
Publication Date:
March 23, 2011
Filing Date:
May 31, 2005
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
G11C16/06
Domestic Patent References:
| JP2001156275A | ||||
| JP10269789A | ||||
| JP2001203331A |
Foreign References:
| WO2002073623A1 | ||||
| US6385097 |
Attorney, Agent or Firm:
Kato Asamichi