マルチプロセッサ・メモリ整合性の効率のよいエミュレーションのための方法 - INTERNATIONAL BUSINESS MASCHINES CORPORATION

Title:

マルチプロセッサ・メモリ整合性の効率のよいエミュレーションのための方法

Document Type and Number:

Japanese Patent JP4658894

Kind Code:

B2

Abstract:

A method (and system) of emulation in a multiprocessor system, includes performing an emulation in which a host multiprocessing system of the multiprocessor system supports a weak consistency model, and the target multiprocessing system of the multiprocessor system supports a strong consistency model.

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Inventors:

Ravi Naia
John Kevin O'Brien
Kathryn Mary O'Brien
Peter Howland Oden
Daniel Arthur Planer

Application Number:

JP2006281049A

Publication Date:

March 23, 2011

Filing Date:

October 16, 2006

Export Citation:

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Assignee:

INTERNATIONAL BUSINESS MASCHINES CORPORATION

International Classes:

G06F9/455; G06F12/08; G06F9/52; G06F12/10; G06F12/14; G06F15/16; G06F15/177; G06F21/60; G06F21/62

Domestic Patent References:

JP11259437A
JP11134307A
JP9506727A
JP8272686A
JP8234981A

Attorney, Agent or Firm:

Takeshi Ueno
Tasaichi Tanae
Yoshihiro City
Hiroshi Sakaguchi

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