Title:
半導体素子の製造方法
Document Type and Number:
Japanese Patent JP4663694
Kind Code:
B2
Abstract:
A semiconductor device and method for manufacturing the same are provided, capable of narrowing feature size by utilizing the property of oxidation of a material. In one method, a polysilicon layer can be patterned into a fine pattern up to a critical dimension using a photolithography process. Then the patterned polysilicon layer can be oxidized, thereby narrowing the gap between adjacent polysilicon patterns and narrowing the polysilicon patterns through the oxidation process. The narrowed polysilicon patterns and/or the narrowed gap between adjacent polysilicon patterns can be used to form vias or trenches in the substrate (or layer) below the polysilicon layer having a width narrower than the critical dimension.
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Inventors:
John, Euns
Application Number:
JP2007204289A
Publication Date:
April 06, 2011
Filing Date:
August 06, 2007
Export Citation:
Assignee:
Dongbu HiTeK Co.,Ltd
International Classes:
H01L21/3205; H01L21/28; H01L21/3065; H01L21/768; H01L29/423; H01L29/49
Domestic Patent References:
| JP2000040739A | ||||
| JP64050531A | ||||
| JP2000012541A | ||||
| JP11031815A |
Attorney, Agent or Firm:
Sakaki Morishita