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Title:
ビデオカメラ
Document Type and Number:
Japanese Patent JP4671625
Kind Code:
B2
Abstract:

To provide a video camera capable of reducing noise mixed in a sound signal drastically, because accurate alignment of a trap frequency can be made.

Noise reduction circuit comprises a first delay unit 104, a first multiplier 105, a second delay unit 106, a second multiplier 107, a adder 108, and an extractor 110. The first delay unit 104 holds a predetermined number of sampling data among the sampling data of sound signals mixed with noise. The first multiplier 105 acquires first sampling data, when the number of sampling data held in the first delay unit 104 reaches the predetermined number and multiplies it by a first factor. Then, the second delay unit 106 acquires second sampling data from the first delay unit 104. The second multiplier 107 acquires the second sampling data from the second delay unit 106 and multiplies it by a second factor. The adder 108 conducts summing processing for the result of the first multiplier 105 and the second multiplier 107. The extractor 110 extracts a noise component based on the result of the adder 108.

COPYRIGHT: (C)2006,JPO&NCIPI


Inventors:
Shinozaki Riku
Application Number:
JP2004159828A
Publication Date:
April 20, 2011
Filing Date:
May 28, 2004
Export Citation:
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Assignee:
Victor Company of Japan, Ltd.
International Classes:
H04N5/232; G10L21/0208; G10L21/0224; G11B20/02; G11B20/24; H04N5/225
Domestic Patent References:
JP2001320794A
JP2000293965A
JP11328884A
JP3226200A
JP11205891A
JP6332288B1
JP6477327A



 
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