Title:
リフレッシュトリガー付き半導体記憶装置
Document Type and Number:
Japanese Patent JP4679528
Kind Code:
B2
Abstract:
A semiconductor memory device includes a memory cell array including a plurality of memory cell transistors, an X decoder designating a position of an X axis of the memory cell, a Y decoder designating a position of a Y axis crossing the X axis, a controller collectively controlling operations of read, write and erase of the memory cell transistors via the X decoder and the Y decoder, a semiconductor time switch generating an output signal after a predetermined life time elapses without a power source, and a refresh trigger circuit receiving the output signal from the semiconductor time switch, and giving the controller instructions to transfer information stored in one area of the memory cell array to other area thereof to refresh the information.
Inventors:
Hiroshi Watanabe
Tatsuya Tanaka
Tatsuya Tanaka
Application Number:
JP2007020016A
Publication Date:
April 27, 2011
Filing Date:
January 30, 2007
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G11C16/02
Domestic Patent References:
| JP2000251483A | ||||
| JP10150171A | ||||
| JP2005141827A | ||||
| JP2004172404A |
Attorney, Agent or Firm:
Hiroshi Horiguchi