Title:
浮遊ゲート型不揮発性半導体メモリ
Document Type and Number:
Japanese Patent JP4679770
Kind Code:
B2
Abstract:
In a floating gate type nonvolatile semiconductor memory having a memory cell array constituted of a plurality of memory cells arrayed in a matrix pattern, word lines and bit lines, with the word lines connected to a row of gate electrodes of memory cells with one cell drain voltage exclusively connected to drain electrodes of either even-numbered memory cells or odd-numbered memory cells among the memory cells through select lines in units of individual rows, another cell drain voltage is connected to the bit lines sequentially via a data write circuit and a multiplexer circuit, the bit lines are each connected to a row of source electrodes of the memory cells and at least two sets each constituted of an data write circuit and a multiplexer circuit are provided with at least one set connected to the ends of the plurality of bit lines on each side.
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Inventors:
Shinichi Murata
Application Number:
JP2001279347A
Publication Date:
April 27, 2011
Filing Date:
September 14, 2001
Export Citation:
Assignee:
oki Semiconductor Co., Ltd.
International Classes:
G11C16/06; G11C16/04; G11C16/12
Domestic Patent References:
| JP2000285689A | ||||
| JP2000306394A |
Attorney, Agent or Firm:
Miaki Kametani
Tetsuo Kanamoto
Koji Hagiwara
Tetsuo Kanamoto
Koji Hagiwara