Title:
集積回路デバイス、集積回路デバイスの製造方法および単一の集積回路にデータとコードとを保存するための方法
Document Type and Number:
Japanese Patent JP4686161
Kind Code:
B2
Abstract:
A memory architecture for an integrated circuit comprises a first memory array configured to store data for one pattern of data usage and a second memory array configured to store data for another pattern of data usage. The first and second memory arrays comprise charge storage based nonvolatile memory cells having substantially the same structure in both arrays. A first operation algorithm adapted for example for data flash applications is used for programming, erasing and reading data in the first memory array. A second operation algorithm adapted for example for code flash applications is used for programming, erasing and reading data in the second memory array, wherein the second operation algorithm is different than the first operation algorithm. Thus, one die with memory for both code flash and data flash applications can be easily manufactured using a simple process, at low cost and high yield.
Inventors:
Leaf everyone
Cai Bun Tetsu
Roh administration
Roh
Cai Bun Tetsu
Roh administration
Roh
Application Number:
JP2004292676A
Publication Date:
May 18, 2011
Filing Date:
October 05, 2004
Export Citation:
Assignee:
Muang Hong Electronic Co., Ltd.
International Classes:
H01L27/10; H01L27/115; G11C11/56; G11C16/04; G11C16/10; G11C16/16; H01L21/8247; H01L29/788; H01L29/792
Domestic Patent References:
| JP2001023382A | ||||
| JP2004039866A |
Foreign References:
| US20020172075 | ||||
| US20040027856 | ||||
| US20040042295 | ||||
| US20030185055 | ||||
| US5953255 | ||||
| US20040047186 | ||||
| US6646924 |
Attorney, Agent or Firm:
Tamio Nishiwaki