To reduce wasteful power consumption by stopping an unnecessary clock during data transfer.

This data transfer circuit comprises a selector 54 for selectively supplying a bus clock BCK or an audio clock ACK to a RAM 20 according to a clock selection signal CLS, and a clock generation circuit 34 capable of stopping output of the bus clock BCK by a clock control signal BCC. When operation of a CPU 1A is unneeded, a FF (Flip Flop) 56 is set by the clock stop signal BCS to stop the operation of the clock generation circuit 34, whereby unnecessary power consumption by wasteful clock supply is reduced. When data in the RAM 20 is completely read out, an interruption signal INT is outputted from an I/F 10A, and the clock generation circuit 34 is activated to restart the operation by the CPU 1A.

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