Title:
半導体素子のトレンチ形成方法
Document Type and Number:
Japanese Patent JP4699691
Kind Code:
B2
Abstract:
The present invention is provided to form a trench in a semiconductor device, wherein by performing an ion implanting process to an area of a semiconductor substrate in which the trench would be formed to cause lattice defects in the area before forming the trench, an etching speed of the area is increased in subsequent trench forming processes. As a result, it is possible to prevent micro trenches from being formed in edge portions of patterns and to suppress a micro loading effect to be generated depending upon pattern sizes.
Inventors:
Yanagi Asahi
Application Number:
JP2003424484A
Publication Date:
June 15, 2011
Filing Date:
December 22, 2003
Export Citation:
Assignee:
MAGNACHIP SEMICONDUCTOR LTD
International Classes:
H01L21/265; H01L21/76; H01L21/3065; H01L21/308; H01L21/762
Domestic Patent References:
| JP2001053138A | ||||
| JP5090401A | ||||
| JP7211893A | ||||
| JP10135321A | ||||
| JP3072652A |
Attorney, Agent or Firm:
Hiroyuki Nakagawa
Sorimachi Yukiyoshi
Yuji Oishi
Kei Iwata
Hiroji Nakagawa
Sorimachi Yukiyoshi
Yuji Oishi
Kei Iwata
Hiroji Nakagawa