Title:
LSIの消費電力ピーク見積プログラム及びその装置
Document Type and Number:
Japanese Patent JP4704299
Kind Code:
B2
Abstract:
As a program tool of the embodiment estimating the peak of power consumption, primary processing is performed in which logic simulation is executed in a first time period to extract operation data of a gated clock for every predetermined section within the first time period, e.g. operation waveform data or data on the number of operations. Then, a narrowed section, which is composed of one or more sections and in which the switching activity per unit time is higher compared to other sections, is discovered, the switching activity being obtained from the operation data, and this narrowed section is taken as a second time period. Then, secondary processing is performed in which logic simulation is executed in the second time period to extract signal waveform data for every clock cycle and obtain power consumption data corresponding to the clock cycles from the extracted signal waveform data.
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Inventors:
Kazuhide Tamaki
Takashi Fujita
Junichi Niizuma
Takayuki Sasaki
Takashi Fujita
Junichi Niizuma
Takayuki Sasaki
Application Number:
JP2006240970A
Publication Date:
June 15, 2011
Filing Date:
September 06, 2006
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F17/50
Domestic Patent References:
| JP2005293163A | ||||
| JP2004287669A | ||||
| JP2003085233A |
Foreign References:
| WO2006133149A2 | ||||
| WO2007037017A1 |
Attorney, Agent or Firm:
Kenji Doi
Hayashi Tsunetoku
Hayashi Tsunetoku