Title:
半導体集積回路
Document Type and Number:
Japanese Patent JP4705493
Kind Code:
B2
Abstract:
In a semiconductor integrated circuit, one of two signals generated from a first logic circuit is delayed in a first delay addition circuit, looped back by an input/output terminal, and then inputted to a second logic circuit. The other output of the first logic circuit is looped back by a reference input/output terminal, further delayed in a second delay addition circuit, and then inputted to the second logic circuit. By varying respective amounts of delay added by the first and second delay addition circuits from each other, AC timing specifications are satisfied and it is determined whether or not the semiconductor integrated circuit has passed a test based on whether or not the output of the second logic circuits is a desired signal relative to the input of the first logic circuit.
Inventors:
Tomoda Masuda
Hiroyuki Sonobe
Masayuki Motohama
Keisuke Kodera
Hiroyuki Sonobe
Masayuki Motohama
Keisuke Kodera
Application Number:
JP2006076272A
Publication Date:
June 22, 2011
Filing Date:
March 20, 2006
Export Citation:
Assignee:
Panasonic Corporation
International Classes:
G01R31/28; H01L21/822; H01L27/04
Domestic Patent References:
| JP4191679A | ||||
| JP2001221834A | ||||
| JP10300817A | ||||
| JP2003179142A |
Attorney, Agent or Firm:
Hiroshi Maeda
Hiroshi Takeuchi
Takahisa Shimada
Yuji Takeuchi
Katsumi Imae
Atsushi Fujita
Kazunari Ninomiya
Tomoo Harada
Iseki Katsumori
Seki Kei
Yasuya Sugiura
Hiroshi Takeuchi
Takahisa Shimada
Yuji Takeuchi
Katsumi Imae
Atsushi Fujita
Kazunari Ninomiya
Tomoo Harada
Iseki Katsumori
Seki Kei
Yasuya Sugiura