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Title:
輪郭強調回路及び輪郭強調方法
Document Type and Number:
Japanese Patent JP4708170
Kind Code:
B2
Abstract:

To provide a contour emphasis circuit and a contour emphasis method that achieve contour emphasis while suppressing occurrence of jaggies.

The contour emphasis circuit EE is composed by serially connecting an interpolator circuit 21, an edge emphasis processing circuit 22, a clipping circuit 23, and a decimeter circuit 24. The interpolator circuit 21 executes up-sampling processing, which increases a sampling rate by executing interpolation, to an inputted signal. Next, the edge emphasis processing circuit 22 executes edge emphasis processing to an up-sampled signal. The clipping circuit 23 executes saturate calculation regarding dynamic range restrictions on output. Next, the decimeter circuit 24 executes down-sampling processing, which reduces the sampling rate by executing thinning-out, to a signal subjected to the edge emphasis processing.

COPYRIGHT: (C)2007,JPO&INPIT


Inventors:
Hiroshi Murase
Minoru Hasegawa
Application Number:
JP2005340756A
Publication Date:
June 22, 2011
Filing Date:
November 25, 2005
Export Citation:
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Assignee:
Ix Co., Ltd.
International Classes:
H04N5/208
Domestic Patent References:
JP9149323A
JP7143365A
JP10208030A
Attorney, Agent or Firm:
Hironobu Onda
Makoto Onda