Title:
導波路ギャップサイズの制御のための微細製造プロセス
Document Type and Number:
Japanese Patent JP4709635
Kind Code:
B2
Abstract:
A method for forming a gap ( 16 ) of a width (d) which meets selected tolerance limits includes forming sidewalls ( 80, 82 ) in a microstructure, the sidewalls defining a gap ( 16 ) therebetween. The gap has a width defined between the sidewalls. The width of the gap between the sidewalls is determined. Where the determined width of the gap is below the selected tolerance limits for the width of the gap, the sidewalls are consumed to form a gap which meets the selected tolerance limits. The gap may be incorporated in a waveguide device ( 10 ) of a microswitch ( 100 ) and selectively connect input and output waveguides ( 130, 132 ).
Inventors:
Pinn Lin
Joel Akaby
Yao Long One
Joel Akaby
Yao Long One
Application Number:
JP2005337889A
Publication Date:
June 22, 2011
Filing Date:
November 22, 2005
Export Citation:
Assignee:
XEROX CORPORATION
International Classes:
G02B26/08; G02B6/26
Domestic Patent References:
| JP2004287431A | ||||
| JP10062625A |
Attorney, Agent or Firm:
Kenji Yoshida
Jun Ishida
Jun Ishida