Title:
パイプライン型A/D変換器
Document Type and Number:
Japanese Patent JP4720842
Kind Code:
B2
Abstract:
A pipeline-type A/D converter includes: N number of stages cascade-connected; and a digital correction circuit that receives digital signals outputted from the N number of stages and outputs a final digital signal. In the converter, an Mth stage in the N number of stages includes: a sub A/D converter A/D-converting an input analog signal; a sub D/A converter D/A converting a digital signal outputted from the sub A/D converter; a differential amplifier circuit that includes a sample hold circuit and an operational amplifier, performs an sampling operation and a holding operation to obtain a difference between the input analog signal and an output signal of the sub D/A converter, and amplifies the difference; and a compensation circuit compensating a gain error of the operational amplifier in an operation of the differential amplifier circuit, the gain error being caused by parasitic capacitance between an input terminal and an output terminal of the operational amplifier, and 1≰M
Inventors:
Akira Abe
Application Number:
JP2008084188A
Publication Date:
July 13, 2011
Filing Date:
March 27, 2008
Export Citation:
Assignee:
Seiko Epson Corporation
International Classes:
H03M1/14
Domestic Patent References:
| JP2007208815A | ||||
| JP2005252326A |
Other References:
BANG-SUP SONG et al.,"A 12-bit 1-Msample/s Capacitor Error-Averaging Pipelined A/D Converter",IEEE J. of Solid-State Circuits,米国,IEEE,1988年12月,Vol.23, No.6,pp. 1324-1333.
Attorney, Agent or Firm:
Tetsuya Mori
Yoshiaki Naito
Yasuhiro Bono
Yoshiaki Naito
Yasuhiro Bono