Title:
リセスゲートトランジスタ構造及びその形成方法
Document Type and Number:
Japanese Patent JP4738745
Kind Code:
B2
Abstract:
A self-aligned inner gate recess channel in a semiconductor substrate includes a recess trench formed in an active region of the substrate, a gate dielectric layer formed on a bottom portion of the recess trench, recess inner sidewall spacers formed on sidewalls of the recess trench, a gate formed in the recess trench so that an upper portion of the gate protrudes above an upper surface of the substrate, wherein a thickness of the recess inner sidewall spacers causes a center portion of the gate to have a smaller width than the protruding upper portion and a lower portion of the gate, a gate mask formed on the gate layer, gate sidewall spacers formed on the protruding upper portion of gate and the gate mask, and a source/drain region formed in the active region of the substrate adjacent the gate sidewall spacers.
Inventors:
Kim Shinaga
Zhao
Shiki Hiroshi
Chung Tai-e
Zhao
Shiki Hiroshi
Chung Tai-e
Application Number:
JP2004003449A
Publication Date:
August 03, 2011
Filing Date:
January 08, 2004
Export Citation:
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
H01L21/28; H01L29/78; H01L21/336; H01L29/423; H01L29/49
Domestic Patent References:
| JP3087069A | ||||
| JP3241870A | ||||
| JP11307760A | ||||
| JP2000269485A | ||||
| JP2004311977A |
Attorney, Agent or Firm:
Masatake Shiga
Takashi Watanabe
Takashi Watanabe