Title:
メモリシステム
Document Type and Number:
Japanese Patent JP4745356
Kind Code:
B2
Abstract:
A memory system includes a WC 21 from which data is read out and to which data is written in sector units by a host apparatus, an FS 12 from which data is read out and to which data is written in page units, an MS 11 from which data is read out and to which data written in track units, an FSIB 12a functioning as an input buffer for the FS 12, and an MSIB 11a functioning as an input buffer to the MS 11. An FSBB 12ac that has a capacity equal to or larger than a storage capacity of the WC 21 and stores data written in the WC 21 is provided in the FSIB12a. A data managing unit 120 that manages the respective storing units suspends, when it is judged that one kind of processing performed among the storing units exceeds predetermined time, the processing judged as exceeding the predetermined time and controls the data written in the WC 21 to be saved in the FSBB 12ac.
Inventors:
Junji Yano
Hidenori Matsuzaki
Kosuke Hatsuda
Hidenori Matsuzaki
Kosuke Hatsuda
Application Number:
JP2008051477A
Publication Date:
August 10, 2011
Filing Date:
March 01, 2008
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G06F12/08; G06F12/00; G06F12/02; G11C16/02
Domestic Patent References:
| JP2006011818A | ||||
| JP2008033788A | ||||
| JP2010521718A | ||||
| JP2009211229A | ||||
| JP2009211220A | ||||
| JP2009211217A | ||||
| JP2009211227A |
Attorney, Agent or Firm:
Hiroaki Sakai