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Patent Searching and Data


Title:
半導体装置の作製方法
Document Type and Number:
Japanese Patent JP4748967
Kind Code:
B2
Abstract:

To provide a technology by which a detailed and highly reliable multilayer wiring structure can be easily formed.

A multilayer wiring structure is obtained by electrically connecting a lower layer wiring with an upper layer wiring arranged at an upper part of the lower wiring via an insulating layer through a protrusion provided at the lower layer wiring. The protrusion is formed at a cylindrical conductive member and upper and lower layers thereof and is configured by a conductive layer formed over the whole lower layer wiring, and the upper layer wiring is electrically connected with the lower layer wiring at a place where the protrusion is exposed on almost the same plane as an upper plane of the insulating layer.

COPYRIGHT: (C)2005,JPO&NCIPI


Inventors:
Akira Ishikawa
Tetsuji Yamaguchi
Application Number:
JP2004311126A
Publication Date:
August 17, 2011
Filing Date:
October 26, 2004
Export Citation:
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Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
H01L21/768; H01L51/50; H01L21/3205; H01L23/52; H01L29/786; H05B33/14
Domestic Patent References:
JP8306779A
JP8181213A
JP2168625A
JP2000012683A
JP8274164A